Electroneum
variant4_random_math.h File Reference

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Classes

struct  V4_Instruction
 

Macros

#define FORCEINLINE   inline
 
#define UNREACHABLE_CODE
 
#define V4_EXEC(i)
 
#define V4_EXEC_10(j)
 

Typedefs

typedef uint32_t v4_reg
 

Enumerations

enum  V4_Settings {
  TOTAL_LATENCY = 15 * 3, NUM_INSTRUCTIONS_MIN = 60, NUM_INSTRUCTIONS_MAX = 70, ALU_COUNT_MUL = 1,
  ALU_COUNT = 3
}
 
enum  V4_InstructionList {
  MUL, ADD, SUB, ROR,
  ROL, XOR, RET, V4_INSTRUCTION_COUNT = RET
}
 
enum  V4_InstructionDefinition { V4_OPCODE_BITS = 3, V4_DST_INDEX_BITS = 2, V4_SRC_INDEX_BITS = 3 }
 

Macro Definition Documentation

◆ FORCEINLINE

#define FORCEINLINE   inline

Definition at line 67 of file variant4_random_math.h.

◆ UNREACHABLE_CODE

#define UNREACHABLE_CODE

Definition at line 77 of file variant4_random_math.h.

◆ V4_EXEC

#define V4_EXEC (   i)

◆ V4_EXEC_10

#define V4_EXEC_10 (   j)
Value:
V4_EXEC(j + 0) \
V4_EXEC(j + 1) \
V4_EXEC(j + 2) \
V4_EXEC(j + 3) \
V4_EXEC(j + 4) \
V4_EXEC(j + 5) \
V4_EXEC(j + 6) \
V4_EXEC(j + 7) \
V4_EXEC(j + 8) \
V4_EXEC(j + 9)
#define V4_EXEC(i)

Typedef Documentation

◆ v4_reg

typedef uint32_t v4_reg

Definition at line 5 of file variant4_random_math.h.

Enumeration Type Documentation

◆ V4_InstructionDefinition

Enumerator
V4_OPCODE_BITS 
V4_DST_INDEX_BITS 
V4_SRC_INDEX_BITS 

Definition at line 46 of file variant4_random_math.h.

◆ V4_InstructionList

Enumerator
MUL 
ADD 
SUB 
ROR 
ROL 
XOR 
RET 
V4_INSTRUCTION_COUNT 

Definition at line 27 of file variant4_random_math.h.

28 {
29  MUL, // a*b
30  ADD, // a+b + C, C is an unsigned 32-bit constant
31  SUB, // a-b
32  ROR, // rotate right "a" by "b & 31" bits
33  ROL, // rotate left "a" by "b & 31" bits
34  XOR, // a^b
35  RET, // finish execution
37 };

◆ V4_Settings

Enumerator
TOTAL_LATENCY 
NUM_INSTRUCTIONS_MIN 
NUM_INSTRUCTIONS_MAX 
ALU_COUNT_MUL 
ALU_COUNT 

Definition at line 7 of file variant4_random_math.h.

8 {
9  // Generate code with minimal theoretical latency = 45 cycles, which is equivalent to 15 multiplications
10  TOTAL_LATENCY = 15 * 3,
11 
12  // Always generate at least 60 instructions
14 
15  // Never generate more than 70 instructions (final RET instruction doesn't count here)
17 
18  // Available ALUs for MUL
19  // Modern CPUs typically have only 1 ALU which can do multiplications
20  ALU_COUNT_MUL = 1,
21 
22  // Total available ALUs
23  // Modern CPUs have 4 ALUs, but we use only 3 because random math executes together with other main loop code
24  ALU_COUNT = 3,
25 };