CIM_ProcessorCapabilities¶
Subclass of CIM_EnabledLogicalElementCapabilities
ProcessorCapabilities inherits the capabilities of EnabledLogicalElementCapabilities and adds properties describing processor core and hardware thread support.
Key properties¶
Local properties¶
string[]
InstructionSetExtensionName
Identifies the instruction set extensions of the processor within a processor architecture, for programmatic use, using a structured string value (termed ‘extension string value’).
Instruction set extensions provide instructions or capabilities in addition to instructions or capabilities provided by the instruction set that is being extended.
The format for extension string values shall conform to the ‘extension’ ABNF rule:
extension = org-id “:” arch-id “:” extension-id
org-id = IDENTIFIER
arch-id = INST-IDENTIFIER
extension-id = INST-IDENTIFIER
Org-id shall include a copyrighted, trademarked, or otherwise unique name that is owned by the business entity that defines the instruction set string value, or that is a registered ID assigned to that business entity by a recognized global authority. In addition, to ensure uniqueness, org-id, arch-id and instset-id shall not contain a colon (:). The business entity that defines the extension string value does not need to own or maintain the definition of the instruction set extension identified by the string value.
Instset-id shall be unique within org-id.
Arch-id shall be unique within org-id.
IDENTIFIER is defined in DSP0004.
INST-IDENTIFIER is defined in the description of the ProcessorArchitecture property.
Extension string values defined by DMTF shall have an org-id of ‘DMTF’ and are all defined in the ValueMap of this property.
In addition to the values defined in its ValueMap, this property may have values not defined in its ValueMap. Subclasses may override the ValueMap (and Values) qualifiers to add additional values.
This array shall be index-correlated with the InstructionSetExtensionStatus array.
The following older x86 instruction set features are not supported by the ValueMap of this property:
- 3DNowPrefetch: PREFETCH and PREFETCHW instruction support
- CLFSH: CLFLUSH instruction support
- CMOV: conditional move instructions
- CMPXCHG8B: CMPXCHG8B instruction
- DE: debugging extensions
- FXSR: FXSAVE and FXRSTOR instructions
- LM: long mode
- LahfSahf: LAHF and SAHF instruction support in 64-bit mode
- MCA: Machine check architecture
- MCE: Machine check exception
- MONITOR: MONITOR/MWAIT instructions
- MSR: AMD model-specific registers, with RDMSR and WRMSR instructions
- MTRR: memory-type range registers
- OSXSAVE: XSAVE (and related) instructions are enabled
- PAE: physical-address extensions
- PAT: page attribute table
- PGE: page global extension
- POPCNT: POPCNT instruction
- PSE: page-size extensions
- PSE36: page-size extensions
- RDTSCP: RDTSCP instruction
- SSE: SSE instructions (prefetch subset)
- SKINIT: SKINIT and STGI are supported
- SysEnterSysExit: SYSENTER and SYSEXIT instructions
- TSC: Time Stamp Counter. RDTSC and RDTSCP instruction support
- VME: Virtual-Mode Enhancements
- WDT: Watch Dog Timer support
- XSAVE: XSAVE (and related) instructions are supported by hardware.
ValueMap Values DMTF:x86:3DNow x86 3DNow: AMD 3DNow! instructions DMTF:x86:3DNowExt x86 3DNowExt: Extensions to AMD 3DNow! instructions DMTF:x86:ABM x86 ABM: Advanced Bit Manipulation instructions: LZCNT DMTF:x86:AES x86 AES: Advanced Encryption Standard instructions: AES*, PCLMULQDQ DMTF:x86:AVX x86 AVX: Advanced Vector Extensions DMTF:x86:AVX2 x86 AVX2: Advanced Vector Extensions 2 DMTF:x86:BMI x86 BMI: Bit Manipulation Instructions: LZCNT, POPCNT DMTF:x86:CX16 x86 CX16: CMPXCHG16B instruction DMTF:x86:F16C x86 F16C: Half-precision convert instructions DMTF:x86:FSGSBASE x86 FSGSBASE: ? DMTF:x86:LWP x86 LWP: Lightweight Profiling support DMTF:x86:MMX x86 MMX: MMX instructions DMTF:x86:PCLMUL x86 PCLMUL: PCLMUL* instructions DMTF:x86:RDRND x86 RDRND: ? DMTF:x86:SSE2 x86 SSE2: SSE2 instructions DMTF:x86:SSE3 x86 SSE3: SSE3 instructions DMTF:x86:SSSE3 x86 SSSE3: Supplemental SSE3 instructions DMTF:x86:SSE4A x86 SSE4A: SSE4A instructions: EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD DMTF:x86:SSE41 x86 SSE41: SSE4.1 instructions DMTF:x86:SSE42 x86 SSE42: SSE4.2 instructions DMTF:x86:FMA3 x86 FMA3: SSE5 Fused Multiply-Add 3 instructions DMTF:x86:FMA4 x86 FMA4: SSE5 Fused Multiply-Add 4 instructions DMTF:x86:XOP x86 XOP: SSE5 Extended Operation instructions DMTF:x86:TBM x86 TBM: Trailing Bit Manipulation instructions DMTF:x86:VT-d x86 VT-d: Intel Virtualization Technology for Directed I/O DMTF:x86:VT-x x86 VT-x: Intel Virtualization Technology DMTF:x86:EPT x86 EPT: Intel VT-x with Extended Page Tables DMTF:x86:SVM x86 SVM: AMD virtualization (AMD-V, Secure Virtual Machine (SVM)) DMTF:PA-RISC:MAX PA-RISC Multimedia Acceleration eXtensions (MAX) DMTF:PA-RISC:MAX2 PA-RISC Multimedia Acceleration eXtensions v2 (MAX2) DMTF:ARM:DSP ARM DSP enhancement instructions (DSP) DMTF:ARM:Jazelle-DBX ARM Jazelle DBX (Direct Bytecode eXecution) DMTF:ARM:Thumb ARM Thumb mode DMTF:ARM:Thumb-2 ARM Thumb-2 mode DMTF:ARM:ThumbEE) ARM ThumbEE mode (Jazelle RCT (Runtime Compilation Target), Thumb-2EE) DMTF:ARM:VFP ARM Vector Floating Point (VFP) Extension DMTF:ARM:NEON ARM Advanced SIMD Extension (NEON, MPE (Media Processing Engine)) DMTF:ARM:TrustZone ARM Security Extensions (TrustZone Technology) DMTF:MIPS:MDMX MIPS Digital Media eXtension (MDMX) DMTF:MIPS:MIPS-3D MIPS instructions for 3D graphics operations (MIPS-3D) DMTF:Alpha:BWX DEC Alpha Byte/Word Extension (BWX) DMTF:Alpha:FIX DEC Alpha Square-root and Floating-point Convert Extension (FIX) DMTF:Alpha:CIX DEC Alpha Count Extension (CIX) DMTF:Alpha:MVI DEC Alpha Motion Video Instructions (MVI)
uint16
NumberOfProcessorCores
Number of processor cores available for processor. This number would not include cores disabled by hardware and may be obtained from SMBIOS 2.5 Type 4 offset 23h.
string
InstructionSet
Identifies the instruction set of the processor within a processor architecture, for programmatic use, using a structured string value (termed ‘instruction set string value’).
The instruction set should not be used to distinguish instruction set extensions (the InstructionSetExtension property is used for that).
The format for instruction set string values shall conform to the ‘instset’ ABNF rule:
instset = org-id “:” arch-id “:” instset-id
org-id = IDENTIFIER arch-id = INST-IDENTIFIER
instset-id = INST-IDENTIFIER
Org-id shall include a copyrighted, trademarked, or otherwise unique name that is owned by the business entity that defines the instruction set string value, or that is a registered ID assigned to that business entity by a recognized global authority. In addition, to ensure uniqueness, org-id, arch-id and instset-id shall not contain a colon (:). The business entity that defines the instruction set string value does not need to own or maintain the definition of the instruction set identified by the string value.
ValueMap Values DMTF:x86:i386 x86 i386 instruction set DMTF:x86:i486 x86 i486 instruction set DMTF:x86:i586 x86 i586 instruction set DMTF:x86:i686 x86 i686 instruction set DMTF:x86:64 x86 64-bit instruction set DMTF:IA-64:IA-64 IA-64: Intel Itanium Architecture, incl. hardware multithreading and Intel Virtualization Technology (VT-i) DMTF:AS/400:TIMI IBM AS/400 TIMI (Technology Independent Machine Interface, 48-bit) DMTF:Power:Power_2.03 Power ISA v2.03 (incl. IBM POWER5) DMTF:Power:Power_2.04 Power ISA v2.04 DMTF:Power:Power_2.05 Power ISA v2.05 (incl. IBM POWER6) DMTF:Power:Power_2.06 Power ISA v2.06 (incl. IBM POWER7) DMTF:S/390:ESA/390 IBM ESA/390 (ARCHLVL 1, 31-bit) DMTF:S/390:z/Architecture IBM z/Architecture 1 (ARCHLVL 2, 64-bit) DMTF:S/390:z/Architecture_2 IBM z/Architecture 2 (ARCHLVL 3, 64-bit) DMTF:PA-RISC:PA-RISC_1.0 PA-RISC 1.0 (64-bit) DMTF:PA-RISC:PA-RISC_2.0 PA-RISC 2.0 (64-bit) DMTF:ARM:A32 ARM A32 (AArch32, 32-bit) DMTF:ARM:A64 ARM A64 (AArch64, 64-bit) DMTF:MIPS:MIPS_I MIPS I (32-bit) DMTF:MIPS:MIPS_II MIPS II (32-bit) DMTF:MIPS:MIPS_III MIPS III (32-bit) DMTF:MIPS:MIPS_IV MIPS IV (32-bit) DMTF:MIPS:MIPS_V MIPS V (32-bit) DMTF:MIPS:MIPS32 MIPS32 (32-bit) DMTF:MIPS64:MIPS64 MIPS64 (64-bit) DMTF:Alpha:Alpha DEC Alpha (64-bit) DMTF:SPARC:SPARC_V7 SPARC V7 (32-bit) DMTF:SPARC:SPARC_V8 SPARC V8 (32-bit) DMTF:SPARC:SPARC_V9 SPARC V9 (64-bit) DMTF:SPARC:SPARC_JPS1 SPARC Joint Programming Specification 1 (64-bit) DMTF:SPARC:UltraSPARC2005 UltraSPARC Architecture 2005 (64-bit) DMTF:SPARC:UltraSPARC2007 UltraSPARC Architecture 2007 (64-bit) DMTF:68k:68000 Motorola 68000/008 (24-bit) DMTF:68k:68010 Motorola 68010/012 (24-bit) DMTF:68k:68020 Motorola 68020 (32-bit) DMTF:68k:68030 Motorola 68030 (32-bit) DMTF:68k:68040 Motorola 68040 (32-bit) DMTF:68k:68060 Motorola 68060 (32-bit)
string
ProcessorArchitecture
Identifies the processor architecture of the processor, for programmatic use, using a structured string value (termed ‘processor architecture string value’).
This property should not be used to distinguish instruction sets or instruction set extensions within a processor architecture; the InstructionSet and InstructionSetExtension properties are used for that.
Different widths of memory addresses should be distinguished via separate processor architecture values if the corresponding instruction set architectures are sufficiently different.
The processor architecture should not designate co-processors that only provide extensions to an instruction set, such as floating point units - these should be represented through instruction set extensions.
The format for processor architecture string values shall conform to the ‘arch’ ABNF rule:
arch = org-id “:” arch-id
org-id = IDENTIFIER
arch-id = INST-IDENTIFIER
INST-IDENTIFIER = 1*( UPPERALPHA / LOWERALPHA / UNDERSCORE / DIGIT / “/” / “-” / “.”)
Org-id shall include a copyrighted, trademarked, or otherwise unique name that is owned by the business entity that defines the processor architecture string value, or that is a registered ID assigned to that business entity by a recognized global authority. In addition, to ensure uniqueness, org-id and arch-id shall not contain a colon (:). The business entity that defines the processor architecture string value does not need to own or maintain the definition of the processor architecture identified by the value.
Arch-id shall be unique within org-id.
IDENTIFIER, UPPERALPHA, LOWERALPHA, UNDERSCORE, DIGIT are defined in DSP0004.
Processor architecture string values defined by DMTF shall have an org-id of ‘DMTF’ and are all defined in the ValueMap of this property.
In addition to the values defined in its ValueMap, this property may have values not defined in its ValueMap. Subclasses may override the ValueMap (and Values) qualifiers to add additional values.
ValueMap Values DMTF:x86 Intel x86 (32-bit, 64-bit: x86-64, x64, AMD64, Intel64) DMTF:IA-64 Intel Itanium Architecture (IA-64, Itanium Processor Architecture (IPA)) DMTF:AS/400 IBM AS/400 Architecture DMTF:Power Power Architecture (incl. POWER, PowerPC, Cell) DMTF:S/390 IBM System/390 and z/Architecture DMTF:PA-RISC HP PA-RISC Architecture DMTF:ARM ARM Architecture DMTF:MIPS MIPS Architecture DMTF:Alpha Intel/DEC Alpha Architecture DMTF:SPARC SPARC Architecture DMTF:68k Motorola 68000 Family
uint16
NumberOfHardwareThreads
Number of hardware threads available for the processor. May be obtained from SMBIOS v2.5 4 offset 25h.
string[]
InstructionSetExtensionStatus
Enablement status of the instruction set extensions specified in the corresponding array elements of the InstructionSetExtensionName property, for programmatic use.
This array shall be index-correlated with the InstructionSetExtensionName array.
ValueMap Values Unknown The enablement status of the extension is unknown Enabled The extension is currently enabled Disabled The extension is currently disabled
Local methods¶
None
Inherited properties¶
string
ElementNameuint16
MaxElementNameLenstring
Captionuint16[]
RequestedStatesSupporteduint64
Generationstring
InstanceIDuint16[]
StateAwarenessboolean
ElementNameEditSupportedstring
ElementNameMaskstring
Description